1. Field of the Invention
The present invention relates to an operating method of a semiconductor device, and more particularly to a reset method of non-volatile memory, which is implemented through a double-side bias band-to-band tunneling hot-hole ((DSB-BTBTHH) effect.
2. Description of Related Art
Electrically erasable programmable non-volatile memory, such as flash memory, is operated usually based on electron injection into a charge-storing layer and electron removal from the same. The electron removal operation is carried out by, for example, ejecting the electrons out of the charge-storing layer or injecting electric holes into the charge-storing layer to combine with the electrons.
Such a memory is operated mostly in one of the following two modes. In the first mode, the electrons in the charge-storing layers of all memory cells are removed for erasing, and electrons are injected into the charge-storing layers of a part of the cells for programming. In the second mode, electrons are injected into the charge-storing layers of all cells for erasing, and the electrons in the charge-storing layers of a part of the cells are removed for programming.
Because the erasing is performed to all cells in the above two modes, the cells preset to the erased state before the erasing are over-erased in the erasing. Thus, for a non-volatile memory operated in the first mode, a certain amount of positive charges exists in the charge-storing layers of a part of the cells after a certain number of the programming/erasing cycles, which results in a leakage issue. On the other hand, for a non-volatile memory operated in the second mode, excess electrons are stored in the charge-storing layers of a part of the cells after a certain number of the programming/erasing cycles, which leads to overly high threshold voltages. Hence, reading/writing error tends to take place in subsequent use of the non-volatile memory device.
To solve said issue, a reset operation is required after the non-volatile memory is used for certain time to make all the memory cells have similar threshold voltages. A conventional reset method is usually performed making the threshold voltages of all the cells around the predetermined threshold voltage of the high-Vt state or the low-Vt state. However, with such a reset method, the variation between the threshold voltages of all the cells is not small enough so that the possibility of reading/writing error cannot be effectively reduced.